vhdl std_logic_vector bit assignment

How to create a signal vector in VHDL: std_logic_vector

The std_logic_vector type can be used for creating signal buses in VHDL. The std_logic is the most commonly used type in VHDL, and the std_logic_vector is the array version of it.

While the std_logic is great for modeling the value that can be carried by a single wire, it’s not very practical for implementing collections of wires going to or from components. The std_logic_vector is a composite type, which means that it’s a collection of subelements. Signals or variables of the std_logic_vector type can contain an arbitrary number of std_logic elements.

This blog post is part of the Basic VHDL Tutorials series.

The syntax for declaring std_logic_vector signals is:

where <name> is an arbitrary name for the signal and <initial_value> is an optional initial value. The <lsb> is the index of the least significant bit, and <msb> is the index of the most significant bit.

The to or downto specifies the direction of the range of the bus, basically its endianness. Although both work equally well, it’s most common for VHDL designers to declare vectors using downto . Therefore, I recommend that you always use downto when you declare bit vectors to avoid confusion.

The VHDL code for declaring a vector signal that can hold a byte:

The VHDL code for declaring a vector signal that can hold one bit:

The VHDL code for declaring a vector signal that can hold zero bits (an empty range ):

In this video tutorial, we will learn how to declare std_logic_vector signals and give them initial values. We also learn how to iterate over the bits in a vector using a For-Loop to create a shift register :

The final code we created in this tutorial:

The waveform window in ModelSim after we pressed run, and zoomed in on the timeline:

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In this exercise we declared six std_logic_vector buses, each eight bits long (one byte).

Signal Slv1 was declared without a initial value. The bus is seen having the value XX in the waveform screenshot. This is because the value that is displayed on the bus is in hexadecimals, and XX indicates a non-hex value. But when we expanded the bus in the waveform, we could see that the individual bits were indeed U’s.

Signal Slv2 was declared using an initial value of all 0’s. Instead of specifying the exact value for each bit, we used (other => '0') in place of the initial value. This is known as an aggregate assignment. The important part is that it will set all bits in the vector to whatever you specify, no matter how long it is.

Signal Slv3 was declared using an aggregate assignment to give all bits the initial value of 1. We can see FF displayed on this signal in the waveform, which is hex for eight 1’s.

Signal Slv4 was declared with an initial value specified in hex, AA. Each hex digit is 4 bits long, therefore we must supply two digits (AA) for our vector which is 8 bits long.

Signal Slv5 declares exactly the same initial value as Slv4 , but now we specified it as the binary value 10101010. We can see from the waveform that both signals have the hex value AA.

Signal Slv6 was declared with an initial value of all zeros, except for the rightmost bit which was '1' . We used a process to create a shift register from this signal. The shift register, as the name implies, shifts the contents of the vector one place to the left every 10 nanoseconds.

Our process wakes up every 10 ns, and the For-Loop shifts all bits in the vector one place to the left. The final bit is shifted back into the first index by the Slv6(Slv6'right) <= Slv6(Slv6'left); statement. In the waveform we can see the '1' ripple through the vector.

By using the 'left' and 'right attributes, we made our code more generic. If we change the width of Sig6 , the process will still work. It’s good design practice to use attributes where you can instead of hardcoding values.

You may be wondering if there are more attributes that you can use, and there are . I won’t be talking more about them in this tutorial series, because I consider them to be advanced VHDL features.

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• N-bit vectors should be declared using std_logic_vector(N-1 downto 0)
• A vector can be assigned as a whole or bits within it can be accessed individually
• All bits in a vector can be zeroed by using the aggregate assignment (others => '0')
• Code can be made more generic by using attributes like 'left and 'right

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I’m from Norway, but I live in Bangkok, Thailand. Before I started VHDLwhiz, I worked as an FPGA engineer in the defense industry. I earned my master’s degree in informatics at the University of Oslo.

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18 Comments

Hi! Excellent article. I have a question, why would you ever use std_logic_vector(0 downto 0) instead of just std_logic?

I have seen std_logic_vector(0 downto 0) being used for mapping a std_logic to a module that has a vector with generic width as an input. Consider this port declaration:

If we want to use a std_logic as input here, we need to first convert it to a std_logic_vector .

In deep logic where generics are used, you may also encounter the zero-width bus. That is, when generics causes a bus to evaluate to this: std_logic_vector(-1 downto 0) . It is legal, but it is also a source of synthesis warnings. For example this warning message from Vivado:

"WARNING: [Synth 8-3919] null assignment ignored"

Hey, I would like to thank you for these tutorials, it not easy to find short and well-explained VHDL lessons nowadays.

I’m glad you found the tutorials helpful. Stay tuned for more advanced topics about VHDL on the blog in the upcoming weeks and months.

Hi sir, i want to take values to array of bit vector from my input bit stream how can i assign? i can not do it by slicing of my array and assigning input value. then how can i do the same

Hi Archana,

To deserialize data that is arriving over a one-bit interface, you can clock the data into a shift register like I’m doing in this blog post. Read out the data word (or byte) when the shift register is full.

The other method is to assign the received bits directly to the correct index in the receive buffer.

Either way, you will have to count the number of received bits to keep track of the position within the received word. You should implement a simple state machine with a counter to take care of this.

Thank you sir..

I have a signal of type “” type ram is array( 0 to 15) of bit_vector(3 down to 0);”” and i have to read elements from text file to this . how can i do this? i am using Textio library. now i am doing it by creating individual 16 signals of bit_vector(3 down to 0) and read the file text to this from the variable and then assigning four such signal to input of type ram is array( 0 to 15) of bit_vector(3 down to 0); like,

how can i do the same by avoiding these steps?

Oh, I see. You want to initialize a RAM from a text file. In the example below, I am initializing your RAM in the declarative region of the VHDL file by using an impure function.

I’ve used your types and signal names. First, we declare the type. Then, we declare an impure function which reads the bits from the data.txt file. Finally, we use the return value from the function as an initial value for the indata1 RAM signal.

Thank You Sir.

I would also like to say that your website has been very helpful! Thanks for all of your efforts on the website and also for any input on my question below, if you have time.

Is it possible to create a port with mixed inputs and outputs other than using inout? That generates a lot of warnings which doesn’t hurt anything however I usually try to avoid warning.

Hello Steve,

A common way to handle this is to declare a local copy of the output signal. Look at the example below to see what I mean.

Thanks for your reply!

I was hoping to have a single “Bus name” in the entity port list with some of the signals in the bus being inputs and others being outputs.

I might be misinterpreting your response or my question might not be clear. Either way, thanks for your time and if you have any additional suggestions, feel free to post them but if not, no worries. Warnings really don’t matter but I prefer to avoid them.

For example: – CPLD_B2:26 – CPLD_B2:01 are dedicated outputs – CPLD_B2:27 is a dedicated input.

I can assign them “inout” but warnings are generated as follows:

Following 27 pins have no output enable or a GND or VCC output enable Info (169065): Pin CPLD_B2[1] has a permanently enabled output enable File.

Oh, I see. That’s only possible in VHDL-2019. Unfortunately, not all FPGA tools support the newest VHDL revision yet. You can read about the change here: https://vhdlwhiz.com/vhdl-2019/#interfaces

Thanks and keep up the great website!

Could you shed some light on toggling multiple bits in a logic vector at the same time?

Hello Sankalp,

You can use a For loop to flip every bit in the vector:

Would this vhdl code be on an infinite loop? Continuously shifting the 1 left?

Hello Jareb,

I wouldn’t consider the shift register process to be an infinite loop because there is a wait for 10 ns; statement inside of it. But I guess from a software perspective, it is an infinite loop because it never stops.

After the simulator executes the last line of a process without a sensitivity list, it immediately continues from the first line again. That’s why we always need to have a Wait statement inside of the process, or we have to use a sensitivity list.

Try to remove the Wait statement from the process and simulate! You will see ModelSim complaining because it’s an infinite loop that continues without any time passing.

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setting single bit in std_logic_vector

• Thread starter c_rpg
• Start date Jan 29, 2012
• Jan 29, 2012

Newbie level 3

I need to set and clear one bit in a large std_logic_vector, the position of the bit that needs to be changed is not static. I have these signals: Code: signal large_vector : std_logic_vector(299 downto 0); signal position : std_logic_vector(8 downto 0); And have tried: Code: large_vector(conv_integer(unsigned(signal position))) <= '1'; But this doesn't work and I also think it will infer a latch because not all bits are assigned. What is the proper way to set or clear this single bit?  

Advanced Member level 2

c_rpg said: I need to set and clear one bit in a large std_logic_vector, the position of the bit that needs to be changed is not static. I have these signals: Code: signal large_vector : std_logic_vector(299 downto 0); signal position : std_logic_vector(8 downto 0); And have tried: Code: large_vector(conv_integer(unsigned(signal position))) <= '1'; But this doesn't work and I also think it will infer a latch because not all bits are assigned. What is the proper way to set or clear this single bit? Click to expand...

Thanks for your reply. The assignment is done in a clocked process like the one you've shown. What I meant with not working was in the specific context of my code. The large vector represents squares on a vga display. They wouldn't show up correctly, but I think the problem was incorrect initialization.  

Advanced Member level 4

c_rpg said: I need to set and clear one bit in a large std_logic_vector, the position of the bit that needs to be changed is not static. Click to expand...

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An Introduction to VHDL Data Types

In this post, we talk about the most commonly used data types in VHDL . We will also look at how we perform conversions between these types.

VHDL is considered to be a strongly typed language. This means every signal or port which we declare must use either one of the predefined VHDL types or a custom type which we have created.

The type which we use defines the characteristics of our data. We can use types which interpret data purely as logical values, for example. We can also use types which interpret our data as if it were a numeric value.

Whenever we assign data to a signal, the data which we assign must adhere to the rules of the types. The code will not compile correctly if we attempt to mix incompatible data types. As a result, it is often necessary to explicitly perform type conversions in VHDL.

Basic VHDL Types

With a few exceptions, every signal or port in a VHDL design fundamentally consists of one or more logical bits. We use the different types in VHDL to tell our tools how this collection of bits should be interpreted.

This means that the simplest type we can use in VHDL consists of a single logical bit. There are actually two different types we can use for this purpose.

Let's take a closer look at both of these types.

• bit Type in VHDL

The bit type is the simplest of all types in VHDL. We use this type to model a single logical value within our FPGA. The bit type can only ever have a value or either 1b or 0b.

The code snippet below shows the method we use to declare a bit type signal in VHDL.

When we assign single bit data types, we use apostrophes (') to represent the data. For example, if we want to set a single bit to 1b we would assign it to '1' in our code.

In the post on entities and architectures in VHDL , we saw how we use signals to model connections in our design. When we assign data to signals we use the <= symbol. We also use this symbol when assigning data to a port.

In VHDL, we can also use variables to model wires in our design. When we assign data to a variable we use the := symbol. We discuss variables in more depth in the post on VHDL process blocks .

The code snippet below shows how we can assign values to a signal or port which uses the bit type.

std_logic Type in VHDL

The other type which we can use to model a single bit in our FPGA is the std_logic type. Although this is similar to the bit type, we have a greater range of values which we can assign to our signal when we use this type.

The code snippet below shows how we declare a std_logic type signal in VHDL.

In a digital circuit, we are mainly concerned with binary data . However, we can also use drivers which set signals to values other than 0b or 1b. It is possible to drive the output of an FPGA pin to high impedance , for example.

The std_logic type attempts to capture this broader range of possibilities. In addition to this, it also models conditions where the logic value is unpredictable. This typically occurs due to errors in our design.

The table below shows the full list of values that the std_logic type can take in VHDL.

As with the bit type, we assign data to a std_logic type signal using apostrophes (') to represent the data. The code snippet below shows how we can assign values to a signal or port which uses the std_logic type.

• Uninitialised or Unknown Values

The std_logic type not only lets us model high impedance signals but also models unknown values. We can get unknown or uninitialised values in our design under two circumstances.

The first circumstance is the simplest to understand. If we have signals in our design which aren't assigned a value at the start of simulation, they will show as uninitialized until they are assigned data.

In the screen shot below we can see how an uninitialized signal looks in a simulation environment. This screen shot is taken from the Vivado design tool which shows the uninitialized signals in the design as orange in the wave viewer.

In this instance, the design uses a PLL to generate the internal clock signals. We can see here that the error signal is uninitialized until the PLL starts outputting a clock.

The second case when we can get unknown values occurs when we drive a signal from more than one source. As an example, consider the simple circuit diagram below which features 2 D type flip flops driving the same wire.

We should never intentionally design a digitial circuit which connects the output of 2 flip flops like this. The reason for this is that the behaviour of the circuit is not deterministic .

To demonstrate this, what would we expect the value of the signal to be if one fo the flip flops drove the output to 1b and the other drove it to 0b?

Actually, the answer is that we simply don't known. If we can't answer this question then it is quite clear that we have non-deterministic behaviour in our circuit.

When we write VHDL code, it is possible to create a non-deterministic circuit such as this one. This typically occurs if we assign data to a signal in more than one concurrent statement or process . This would lead to a signal which has an unknown value as our simulator can't determine what binary value it will actually take.

• Resolving std_logic Signals

When we design a digital circuit, there are occasions when we need to use circuits which have multiple drivers. For example, we may declare a port as an inout type so that we can use a bidirectional bus connected to an external flash device.

In VHDL, the std_logic type uses a concept known as resolution to allow us to use signals with multiple drivers.

To understand how resolution works in VHDL, we need to consider the drive strength of a signal. In a physical circuit, drive strength refers to the maximum amount of current it can deliver. A weak pull-up resistor can obviously deliver much less current than a MOSFET could.

The resolution function models this concept of drive strength to determine what value a signal should take when it is driven by multiple sources. To do this, a different effective drive strength is assigned to each of the possible states that a std_logic type can take.

When we drive a signal with two different values, the state with the highest drive strength takes precedent.

If we drive the signal with a mixture of '0' and '1' then the signal is assigned to the unknown ('U') state. This is because the '0' and '1' states have the same effective drive strength. When we use a mixture of the 'L' and 'H' states, the signal resolves to 'W' rather than 'U'.

The table below shows the modelled drive strength of the different std_logic states.

The code snippet below gives some basic examples which demonstrate the functionality of the resolution function.

• std_logic vs bit Type

Although we use the bit type and std_logic type to model the exact same thing in our design, the std_logic type is much more commonly used.

The main reason for this is that it provides a more realistic model of signals in a digital system. This is largely because it allows us to model various high impedance states.

Another advantage of the std_logic type is that the uninitialised state makes it easier to find signals which are not correctly driven. This is especially useful for finding bugs in circuits which feature a reset value.

Despite this, one advantage that the bit type has it that it will cause a compilation error when we design a circuit which features multiple drivers. In contrast to this, the std_logic type will compile code with multiple drivers.

However, it is normally easy to find bugs which arise due to the use of multiple drivers during simulation. This explains why the extra flexibility of the std_logic type makes it a more popular choice than the bit type despite this draw back.

There is also a std_ulogic type in VHDL which causes compilation errors when using multiple drivers. However, this type has no resolution function and is less commonly used that the std_logic type as a result.

VHDL Vector Types

The two types which we have looked at so far allow us to model single bits in our VHDL designs. However, we often use data buses which consist of multiple bits when we design digital circuits.

In VHDL, we can use vector types to model multiple bit buses. These vectors all consist of a number of bits which are modeled in a similar way to the std_logic or bit types.

Let's take a closer look at the most commonly used vector types in VHDL.

std_logic_vector and bit_vector Types

The most basic type of vector we can use in VHDL are made up of a number of bit or std_logic types. The code snippet below shows how we declare a vector type signal in VHDL.

The <range> field is used to determine the number of bits in the vector and the location of the most significant and least significant bits . We use the downto and to keywords to describe the range value in VHDL.

When we use the downto keyword, the msb is the left most bit in the signal. When we use the to keyword, the msb is the right most bit of the signal. The code snippet below shows how we would declare an 8 bit signal using both keywords.

• Assigning Data Values

When we assign data to vector types in VHDL we use quotation marks (") instead of apostrophes. We can also specify data using hexadecimal notation by appending an x to the start of the data. However, this only works if the number of bits in the vector is a factor of four.

The code snippet below gives some examples of how we assign data to vector types in VHDL.

When we are working with the VHDL-2008 standard we can also assign vector data using an octal number. This works in the same way as hex formatted data except we must replace the x with an o. The code snippet below gives an example of this.

We can also assign data to slices or single bits of the vector. To do this we must specify the range of bits we are assigning. The code snippet below shows the general syntax for this.

The <range> field in the above code snippet uses either the downto or to keyword to specify the slice we are assigning. It works in the exact same as the range field we talked about when declaring a vector type signal .

If we want to assign a single bit of the vector then we replace the range value with the index of the bit. However, in this case we must remember that we are assigning a single bit of data. This means that the data value must be enclosed by apostrophes rather than quotation marks.

The VHDL code snippet below shows some examples of assigning data to slices of a std_logic_vector type.

When we use bit slicing in this way, we will get compilation errors if we use an invalid range. For example, if we attempt to assign four bit data to a 3 bit slice this will cause an error.

Finally, there is one more useful function which we can use in VHDL to assign all of the bits of a vector to 1 or 0. We use the others keyword for this, as shown in the code snippet below.

• Signed and Unsigned VHDL Types

There are two more vector types which we often use in VHDL - signed and unsigned. In order to use these types, we need to include the numeric_std package from the standard ieee library.

When we use the signed type, the data is interpreted as a 2's complement number . This is in contrast to the unsigned type which is a normal binary number. This means that we can assign negative values to the signed type but not the unsigned type.

The VHDL code snippet below shows the general syntax for declaring a signal of both signed and unsigned type.

The signed and unsigned types are similar to the std_logic_vector type. However, we can also perform maths operations on them. In addition to this, we can also assign numerical data to them.

The code snippet below shows the two ways we can assign a value of four. This shows how it is possible to assign data either as a binary value or a base 10 integer type value.

The ieee.numeric_std VHDL library defines a number of mathematical operators which we can use with the signed and unsigned types. The table below shows the arithmetic operators we can use with these types.

The code snippet below shows how we use each of these arithmetic operators in practise.

These arithmetic operators require some consideration when we use them with synthesizable code though.

The plus, minus and multiplication operators can all be synthesized by most modern tools. However, this can often result in sub-optimal logical performance. As a result, it can be necessary to design logic circuits which specifically perform these functions.

We should never use the modulus or divide operators for synthesizable code as most tools will be unable to handle them.

• Integer Type

The integer data type is used to express a value which is a whole number in VHDL. This is similar to the integer type in other programming languages such as C.

The code snippet below shows the general syntax for declaring an integer type signal in VHDL. The <range> field is optional and we use this to limit the values the range of values integer can take in our VHDL design.

The integer type is similar to both the signed and unsigned types . We can use the integer type to express numbers and perform basic arithmetic operations.

The table below shows the mathematical operators we can use with the integer type.

We don't directly deal with bits when we are working with the integer type in VHDL. This is one of the key defining features which separates it from the signed and unsigned types.

As a result of this, we can't assign binary, hex or decimal type data to an integer. Instead, we always use a numeric value to assign data.

As with most programming lanaguges, the integer type in VHDL is 32-bits wide by default.

However, we can limit the range of the integer to save resources in our FPGA when writing VHDL code. For example, we may require a signal which counts from 0 to 150. Therefore, we can implement this as an 8 bit integer within our FPGA.

In order to limit the range of the integer, we specify the valid values the integer can take. We use the downto and to VHDL keywords which we have seen before to specify this range.

The code snippet below shows how we would declare an integer signal in VHDL which has a valid range from 0 to 150.

We can also use 2 integer subtypes in VHDL - natural and positive. The positive subtype can take the any positive integer value. The natural type is the same as the positive type except that it can also be assigned to 0.

VHDL Type Conversions

When we write VHDL code, we often have to convert between data types. There are two general methods which are available to us for this.

The first method is to simply cast the signal to the correct type. We can use this method to convert between the signed, unsigned and std_logic_vector VHDL data types.

The code snippet below shows the general syntax which we use to cast signals or data.

The second way we convert VHDL data types is through the use of a function. We normally use this method to convert between the signed or unsigned types and the integer type.

In order to use a suitable conversion function, we need to include either the numeric_std or std_logic_arith packages. Both of these packages are available in the IEEE library.

Although many engineers still use it, the std_logic_arith package is not officially supported by the IEEE standards and we should avoid using it . Therefore, we will only consider the functions which are included in the numeric_std package in this post.

The image below summarises the methods we use to convert between different data types in VHDL.

Let's look in more detail at the way we convert between the different data types in VHDL.

• Convert unsigned to std_logic_vector

To convert an unsigned type to a std_logic_vector we can simply cast the signal. However, whenever we do a cast we need to make sure that the signals have the same number of bits. If we don't do this then we will get an error.

The VHDL code below shows an example of casting the unsigned type to a std_logic_vector type.

• Convert unsigned to signed

As with the unsigned to std_logic_vector conversion, we can simply cast an unsigned type to a signed type. Again, we need to make sure that the signals have the same number of bits.

The code snippet below shows an example of casting the unsigned type to a signed type.

• Convert unsigned to integer

When we want to convert the unsigned type to an integer we have to use the to_integer function. This is a part of the numeric_std package in the ieee library so we must include this library and package in our code.

The code snippet below shows how we would include this library and package in our design.

After we have included the relevant package we can simply call the function to perform the required conversion. The VHDL code below shows an example where we use the to_integer function to convert an unsigned type to an integer.

• Convert signed to std_logic_vector

To convert a signed type to a std_logic_vector we can use a basic cast. We will need to make sure that the two signals have the same number of bits otherwise we will get an error.

The VHDL code below gives an example which shows how we convert the signed type to a std_logic_vector.

• Convert signed to unsigned

As with the signed to std_logic_vector conversion, we can use a simple cast to convert a signed type to an unsigned type. Again, we need to make sure that the signals have the same number of bits.

The code snippet below shows an example of casting the signed type to an unsigned type.

• Convert signed to integer

When we want to convert the signed type to an integer we have to use the to_integer function. This is a part of the numeric_std package in the ieee library so we must include this library and package in our code.

After we have included the relevant package we can simply call the function to perform the required conversion. The VHDL code below shows an example where we use the to_integer function to convert a signed type to an integer.

• Convert std_logic_vector to unsigned

We can use a simple cast to convert a std_logic_vector type into an unsigned type. However, we must take care to ensure that the signals have the same number of bits otherwise we will get an error.

The VHDL code below shows an example of casting a std_logic_vector type to an unsigned type.

• Convert std_logic_vector to signed

We can also use a simple cast to convert a std_logic_vector type into a signed type. Again, we must take care to ensure that the signals have the same number of bits.

The code snippet below shows an example of casting a std_logic_vector type to a signed type.

• Convert std_logic_vector to integer

We can't directly convert between the std_logic_vector and integer types in VHDL. The reason for this is that VHDL doesn't know how to interpret the std_logic_vector type as a numerical value.

To overcome this problem, we must firstly cast the std_logic_vector to either a signed or unsigned type. We can then use the to_integer function from the numeric_std package to convert the signed or unsigned type to an integer.

The code snippet below shows how we would include the ieee library and numeric_std package in our design.

The VHDL code below shows how we would convert a std_logic_vector to an integer. It is quite typical to see the cast and the function call in one line as shown in the example below.

• Convert integer to unsigned

To convert an integer type to an unsigned type, we use the to_unsigned function. This is a part of the numeric_std package in the ieee library so we must include this library and package in our code

The to_unsigned function take two arguments. The first is the integer value which we want to convert to an unsigned type.

The second argument is the number of bits in the resultant unsigned signal. We typically use the length attribute to calculate this automatically for us.

The code snippet below shows the general syntax for the to_unsigned function.

The VHDL example below shows how we use the to_unsigned function to convert an integer to an unsigned type.

• Convert integer to signed

To convert and integer type to a signed type, we use the to_signed function. This is a part of the numeric_std package in the ieee library so we must include this library and package in our code

The to_signed function is similar to the to_unsigned function which we previously discussed. Again, this function takes two arguments.

The first argument is the integer value which we want to convert to a signed type.

The second argument is the number of bits in the resultant signed value. We typically use the length attribute to calculate this automatically for us.

The code snippet below shows the general syntax for the to_signed function.

The VHDL example below shows how we use the to_signed function to convert an integer to a signed type.

• Convert integer to std_logic_vector

We can't directly convert between the std_logic_vector and integer types in VHDL. The reason for this is that VHDL doesn't know how to interpret the std_logic_vector type as a numerical value

To overcome this problem, we must firstly convert the integer to either a signed or unsigned type. We do this using the to_signed and to_unsigned functions which we have previously talked about.

As these functions are a part of the numeric_std package, we must include this in our design. The code snippet below shows how we would include the relevant library and package in our design.

Once we have converted the integer to a signed or unsigned type, we can then cast the resultant signal into a std_logic_vector.

The VHDL code below gives an example which shows how we convert an integer to a std_logic_vector. It is quite typical to see the cast and the function call in one line as shown in the example below.

What is the main difference between the bit and and std_logic types?

The std_logic type can take on more values which allows it to model high impedance states.

What is the difference between the std_logic_vector type and the signed/unsigned types?

We can assign numeric values to the signed and unsigned types. We can also perform arithmetic operations on these types.

Which library and package must we include in our VHDL design if we want to use the signed and unsigned types

The numeric_std package fromt he ieee library

What is the difference between the integer types and the signed/unsigned types?

We can only assign numeric values to integer types whereas we can assign both numeric and binary data to signed and unsigned types.

What is the difference between the integer type and the positive type?

The positive type can only be assigned positive, whole numbers. The integer can also accept negative numbers.

Which function do we use to convert either the unsigned or signed types into an integer. Which library and package do we need to include to use this function.

We use the to_integer function to convert the signed and unsigned types to an integer. This function can be found in the numeric_std package which is a part of the ieee library.

Write some code which converts an 8 bit signed signal to a std_logic_vector, then converts the resultant std_logic_vector to an unsigned type.

Write some VHDL code which converts an integer type to an 8 bit std_logic_vector. The integer should be treated as an unsigned number.

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Simplifying VHDL Code: The Std_Logic_Vector Data Type

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This article will review the "std_logic_vector" data type which is one of the most common data types in VHDL.

In a previous article on the VHDL hardware description language , we discussed the basic structure of VHDL code through several introductory examples. This article will review one of the most common data types in VHDL, i.e., the “std_logic_vector” data type.

We will first discuss the fact that vectors allow us to have a more compact and readable VHDL description, especially when dealing with large circuits. Then, after reviewing some important features of the “std_logic_vector” data type, we will go over some coding styles that can help us avoid mistakes when utilizing vectors.

Why Do We Need Vector Data Types?

Consider the simple circuit in Figure 1, which was discussed in the previous article .

Figure 1. A simple digital circuit.

Here is the VHDL code for this circuit:

Now, assume that we need to write the VHDL code for the circuit in Figure 2.

We can extend the previous code to obtain the VHDL description of Figure 2 as

The above code is correct; however, we will see that it’s possible to have a more compact and readable VHDL description for this circuit. The drawback to the above code is that it presents each of the input/output ports as individual signals and doesn’t establish any relationship between them.

Let’s consider an alternative way of depicting the circuit in Figure 2.

Figure 3 suggests that we can consider a0 , a1 , and a2 as a three-bit input port called, for example, a_vec . Similarly, the input ports b0 , b1 , and b2 can be grouped as another three-bit input port called b_vec . What the circuit does is AND an element of a_vec with a corresponding element of b_vec . This may seem like a simple idea, but we will see in a minute how this way of thinking makes the code more readable.

The “Std_Logic_Vector” Data Type

To represent a group of signals, VHDL uses vector data types. To access an element of a vector, we need to define an index. For example, assume that, as shown in Figure 4, we use a vector of length three, a_vec , to represent three values: val_0 , val_1 , and val_2 . To access the value of an element from this vector, we can use the index numbers. For example, a_vec(2) will give the value of the rightmost element of the vector in Figure 4, which is val_2 .

Figure 4. The three-element vector a_vec.

The VHDL keyword “std_logic_vector” defines a vector of elements of type std_logic. For example,  std_logic_vector(0 to 2) represents a three-element vector of std_logic data type, with the index range extending from 0 to 2.

Let’s use the “std_logic_vector” data type to describe the circuit in Figure 3. We will use three vectors a_vec, b_vec, and out_vec to represent the blue, red, and black ports of Figure 3, respectively. With the new naming for the ports, we obtain the following figure.

The VHDL code for Figure 5 is given below.

Lines 4 to 6 of this code use the “std_logic_vector” data type for the input/output ports of the circuit. Note that the AND operation in line 10 will be applied to the corresponding elements of the two vectors a_vec and b_vec , i.e., a_vec(0) is ANDed with b_vec(0) and the result is assigned to out_vec(0) , and so on. Comparing this with the previous code, we observe that use of the “std_logic_vector” data type allows us to have much more compact and readable code. This advantage becomes particularly evident when dealing with large circuits; just imagine how unwieldy the code would be if we used individual signal-assignment statements for ANDing the elements of two 32-bit vectors.

An ISE simulation of the above code is shown in Figure 6.

Figure 6. ISE simulation of the circuit shown in Figure 5.

Interpreting std_logic_vector data.

There is one important point which needs further attention: As shown in the above example, the “std_logic_vector” data type is a way to represent a group of signals or a data bus. It is simply a string of ones and zeros, and there is no other interpretation for this string of ones and zeros. In other words, if we assign “011” to a_vec , this doesn’t mean that a_vec is equal to 3 (the decimal equivalent of “011”).

We cannot assume a weight for the different bit positions of a “std_logic_vector” signal. However, we can use type conversion functions and type casting to interpret the string of ones and zeros in a given “std_logic_vector” signal as a number. Type conversion will be discussed in a future article.

Ascending or Descending Index Range?

So far, we have used the “std_logic_vector” data type when defining input/output ports. Similarly, we can define a signal of “std_logic_vector” type. As an example, consider the following lines of code:

Here, the first line defines a as a signal of type “std_logic_vector”. The index ranges from 0 to 3. Then, “0010” is assigned to a . With this assignment, as shown in Figure 7, we will have a(0)=0 , a(1)=0 , a(2)=1 , and a(3)=0 .

The indexing style of this vector, which uses the keyword “to”, is called ascending. We can also use the keyword “downto” (instead of “to”) when we want a descending index range:

In this case, as shown in Figure 8, we’ll have a(3)=0 , a(2)=0 , a(1)=1 , and a(0)=0 .

The choice between ascending and descending order is often a question of the designer’s preferences, though it may be addressed by coding guidelines adopted by a particular organization. The most important thing is to choose one style and then follow it consistently; mixing the two different styles in one project can easily lead to trouble.

For example, consider the truth table for a 4-to-2 priority encoder, as given below. With a priority encoder, we generally consider the leftmost bit of the input vector to have the highest priority. For example, in the following truth table, when the leftmost input bit, x(3) , is high, we don’t care about the state of the other three input bits and assert the outputs y and v , i.e., y=“11” and v=‘1’ . 

We observe that this truth table assumes the input vector  x  to have a descending index range because the element with the highest index is placed in the leftmost position. Now, assume that despite choosing a descending index range in the truth table, we use an ascending index range when declaring the input vector  x  and assign “0001” to  x . In other words, we have:

Since the rightmost bit of x is high, considering the general definition for a priority encoder, we expect the outputs y and v to be “00” and ‘1’, respectively. However, with the above code x(3) is high and, based on the above truth table, the output will be y=“11” and v=‘1’ . To avoid such problems, we should use a descending index range consistently throughout the code.

• The “std_logic_vector” data type allows us to have code that is much more compact and readable. This data type provides us with a way to represent a group of signals or a data bus.
• We cannot assume a weight for the different bit positions of a “std_logic_vector” signal. However, we can use type conversion functions and type casting to interpret the string of ones and zeros in a given “std_logic_vector” signal as a number.
• The index range used in a “std_logic_vector” declaration can be either ascending or descending. The former uses the keyword “to”, and the latter uses the keyword “downto”.
• The choice between ascending and descending order is often a question of style, but it is important to apply this choice consistently throughout a particular project.

To see a complete list of my articles, please visit  this page .

Featured image courtesy of Altera .

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Most logic synthesis tools accept one-dimensional arrays of other supported types. 1-D arrays of 1-D arrays are often supported. Some tols also allow true 2-D arrays, but not more dimensions.

Note that arrays are usually implemented using gates and flip-flops, not ROM's and RAM's.

Array types have not changed in VHDL -93.

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VHDL: shift_left or shift_right on a 10-bit std_logic_vector, and assign result to 16-bit std_logic_value? Assigning 10-bit value to 16-bit vector?

Hi all, I'm working on a little project for school, but can't quite figure this out:

I'm trying to halve or double the input of SP_mm, and assign that value to SP_EncoderUnits.

What I want to know is wether 16_bit_vector <= 10_bit_vector is enough to assign the value of a smaller vector to a larger, retaining the numeric value of these bits (ignoring Z, U, X, etc.). In other words, can I assign a 'shorter' value to a std_logic_vector than the defined length of that vector? (and am I doing it right?)

What I also want to know is wether my code shown above is adequate, I'll add full code (what i have so far) in the comments.

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VHDL: Code to put a numeric value in a STD_LOGIC_VECTOR variable

I would like to enter a number in a a variable of type STD_LOGIC_VECTOR but I have problems with the compiler.

The compiler give me these two messages:

• The integer value of 111111111111111 is greater than integer'high.
• Type of cl_output_ChA is incompatible with type of 111111111111111.

could anyone give me a proper code line to put in this variable a particular numeric value? Thank you so much.

• Could anyone create a tag called 'code', this could indicate someone asking for a piece of code. –  Peterstone Commented Jul 14, 2011 at 15:14

2 Answers 2

First of all, the error is because the number as you have written it is treated as an integer.

I take that you mean for the number to be binary? In that case use "".

You can also go for hex, x"".

If you want to assign an integer to an std_logic_vector, then you can do it like this.

Where 12345 is the integer (or natural) and 16 is the width.

• I suposse 16 are the numbers of bits that are needed to represent that number, isn´t it? –  Peterstone Commented Jul 14, 2011 at 18:47
• @Peterstone: Yes, but see my edit which shows a way which will scale if you change the length of your vectors for any reason. –  Martin Thompson Commented Jul 15, 2011 at 12:26
• @Martin, thanks for the edit to add in the 'length attribute. –  George Commented Jul 18, 2011 at 10:38

You could also do the following, which puts a 1 in each bit.

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VHDL: Convert std_logic to std_logic_vector

I'm trying to make a 4 bit adder with carry in & out, but I am having trouble converting Cin (Carry-in) to the type std_logic_vector when summing Sum and Cin together below in the architecture. Do you have any idea how i can make these types fit so that I can perform arithmetic on them together?

EDIT: It was an error that I made Cout a 2 bit std_logic_vector. It should just have been a simple std_logic.

• 1 \$\begingroup\$ Cout is 2 bits wide, which is odd... You are possibly missitg the fact that an array aggregate with one member can't use positional association. So use named association. (0 => Cin) is a 1 bit SLV. \$\endgroup\$ –  user16324 Commented Oct 19, 2019 at 18:45
• \$\begingroup\$ @BrianDrummond You need to add Cin, not concatenate it. So the total line is wrong. \$\endgroup\$ –  user110971 Commented Oct 19, 2019 at 18:53
• \$\begingroup\$ As @BrianDrummond says, Cout looks like it should be corrected to a std_logic output. \$\endgroup\$ –  TonyM Commented Oct 19, 2019 at 18:54
• \$\begingroup\$ If Cout should be an SLV, it should be a 1 bit SLV, e.g. (0 downto 0). And I was merely converting Cin to a SLV. Who mentioned concatenation? \$\endgroup\$ –  user16324 Commented Oct 19, 2019 at 18:58
• 1 \$\begingroup\$ Re: your edit. You still have an error. Your output Sum doesn't take Cin into account. \$\endgroup\$ –  Blair Fonville Commented Oct 19, 2019 at 21:06

3 Answers 3

You need to cast cin to an unsigned, then add it in.

Note that resize returns an unsigned here.

• \$\begingroup\$ To simplify the code above, most type conversion/casting can be avoided by simply giving signals and ports the appropriate numeric type in the first place. \$\endgroup\$ –  scary_jeff Commented Oct 23, 2019 at 8:11

Seeing as to how the question was not actually answered:

The following is a simplification of your design that meets all the requirements and compiles in VHDL-93 onwards. It uses std_logic_unsigned rather than numeric_std. (Forgive the style changes, automatic when I typed and tested it.)

The 5-bit addition is done in one line by first padding each element with leading zeroes.

• 2 \$\begingroup\$ You cannot add std_logic_vectors like that. You need to cast them to a numeric type first. \$\endgroup\$ –  user110971 Commented Oct 19, 2019 at 18:56
• 1 \$\begingroup\$ It doesn’t work. It is only supported in VHDL-2008, but you must use ieee.numeric_std_unsigned. \$\endgroup\$ –  user110971 Commented Oct 19, 2019 at 19:08
• \$\begingroup\$ @user110971 this does work but uses std_logic_unsigned, which is a non-standard package. You are correct that in VHDL-2008 the same functionality has been included in the standard library numeric_std_unsigned. \$\endgroup\$ –  ks0ze Commented Oct 19, 2019 at 20:51
• 1 \$\begingroup\$ @ks0ze My above comment was a reply to a now deleted comment, so it seems confusing. Indeed the edited answer now works, but uses non-standard libraries, which is just bad practice. If you want to avoid excessive casting, you should just use Verilog. VHDL is a strongly typed language, which can be really annoying at times. In fact, I do prefer Verilog. See the original answer for the full context of my comment. \$\endgroup\$ –  user110971 Commented Oct 19, 2019 at 21:30
• 1 \$\begingroup\$ @TonyM Well I know about a case wherein the change of an FPGA vendor almost resulted in someone’s death due to the use of non-standard libraries. Avoid good practice at your own peril. \$\endgroup\$ –  user110971 Commented Oct 19, 2019 at 21:34

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