continuous assignment delay in verilog

Verilog Inter and Intra Assignment Delay

Verilog delay statements can have delays specified either on the left hand side or the right hand side of the assignment operator.

Inter-assignment Delays

An inter-assignment delay statement has delay value on the LHS of the assignment operator. This indicates that the statement itself is executed after the delay expires, and is the most commonly using form of delay control.

Note that q becomes 1 at time 10 units because the statement gets evaluated at 10 time units and RHS which is a combination of a , b and c evaluates to 1.

Intra-assignment Delays

An intra-assignment delay is one where there is a delay on the RHS of the assignment operator. This indicates that the statement is evaluated and values of all signals on the RHS is captured first. Then it is assigned to the resultant signal only after the delay expires.

Note that the assignment to q is missing in the log !

This is because at 5 time units, a and c are assigned using non-blocking statements. And the behavior of non-blocking statements is such that RHS is evaluated, but gets assigned to the variable only at the end of that time step.

So value of a and c is evaluated to 1 but not yet assigned when the next non-blocking statement which is that of q is executed. So when RHS of q is evaluated, a and c still has old value of 0 and hence $monitor does not detect a change to display the statement.

To observe the change, let us change assignment statements to a and c from non-blocking to blocking.

Verilog Continuous Assignment Statements Tutorial

Continuous assignment statements are an essential aspect of Verilog that allows you to assign values to signals without using procedural blocks. Unlike procedural assignments found in always blocks, continuous assignments are used for modeling combinational logic. In this tutorial, we will explore continuous assignment statements in Verilog and learn how to use them to describe the behavior of combinational circuits efficiently.

Introduction to Continuous Assignment Statements

Continuous assignment statements in Verilog are used to specify the relationship between input and output signals in a combinational circuit. They allow you to assign a value to a signal continuously, meaning the assignment is continuously evaluated as the inputs change. Continuous assignments are used outside procedural blocks and are ideal for describing combinational logic or interconnections between signals.

Example of Continuous Assignment Statements:

Another example:, steps to use continuous assignment statements.

To use continuous assignment statements in Verilog, follow these steps:

• Identify the combinational logic relationship between input and output signals.
• Use the 'assign' keyword to create a continuous assignment statement.
• Specify the output signal on the left-hand side and the combinational logic expression on the right-hand side of the assignment.
• Ensure that the right-hand side expression does not contain any procedural constructs, as continuous assignments are not allowed to contain procedural statements.
• Continuous assignments are evaluated in parallel with no explicit sequencing, making them suitable for combinational logic modeling.

Common Mistakes with Continuous Assignment Statements

• Using procedural statements such as if-else or case statements within continuous assignments.
• Missing the 'assign' keyword before the continuous assignment statement, leading to syntax errors.
• Attempting to use continuous assignments for modeling sequential logic, which is not their intended use.
• Using continuous assignments for outputs in modules with procedural assignments, leading to unexpected behavior.
• Not considering the propagation delays of combinational logic when using continuous assignments, which may affect simulation results.

Frequently Asked Questions (FAQs)

• Q: Can I use continuous assignments inside an always block? A: No, continuous assignments are not allowed inside always blocks. They are used outside procedural blocks to model combinational logic.
• Q: What is the difference between continuous assignments and procedural assignments? A: Continuous assignments are evaluated continuously for combinational logic, while procedural assignments in always blocks are used for modeling sequential logic that executes based on clock edges or event triggers.
• Q: Can I use continuous assignments for bidirectional signals? A: No, continuous assignments can only be used for assigning values to output or wire signals, not bidirectional signals or registers.
• Q: How do continuous assignments affect the simulation time of a Verilog design? A: Continuous assignments add negligible overhead to the simulation time as they represent combinational logic and are evaluated in parallel with no explicit sequencing.
• Q: Can I use continuous assignments for modeling arithmetic operations? A: Yes, continuous assignments can be used to model arithmetic operations in combinational logic. For example, you can use continuous assignments to describe the addition or subtraction of signals.
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Continuous Assignment Statement

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A continuous assignment drives a value into a net.

Description:

Continuous assignments model combinational logic. Each time the expression changes on the right-hand side, the right-hand side is re-evaluated, and the result is assigned to the net on the left-hand side.

The implicit continuous assignment combines the net declaration (see Net data type) and continuous assignment into one statement. The explicit assignment require two statements: one to declare the net (see Net data type), and one to continuously assign a value to it.

Continuous assignments are not the same as procedural continuous assignments. Continuous assignments are declared outside of procedural blocks. They automatically become active at time zero, and are evaluated concurrently with procedural blocks, module instances, and primitive instances.

Net data type , Procedural continuous assignment

Modeling Concurrent Functionality in Verilog

• First Online: 01 March 2019

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This chapter presents a set of built-in operators that will allow basic logic expressions to be modeled within a Verilog module. This chapter then presents a series of combinational logic model examples.

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LaMeres, B.J. (2019). Modeling Concurrent Functionality in Verilog. In: Quick Start Guide to Verilog. Springer, Cham. https://doi.org/10.1007/978-3-030-10552-5_3

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Delay in Assignment (#) in Verilog

Syntax : #delay

It delays execution for a specific amount of time, ‘delay’.

There are two types of delay assignments in Verilog:

Delayed assignment: #Δt variable = expression; // “ expression”  gets evaluated after the time delay Δt and assigned to the “variable” immediately Intra-assignment delay: variable = #Δt expression;  // “expression” gets evaluated at time 0 but gets assigned to the “variable” after the time delay Δt

Note: #(delay) can not be synthesized. So we do not use #(delay) in RTL module to create delay. There are other methods which can be used to create delays in RLT module. #(delay) can be used in testbench files to create delays.

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Related posts:

• Blocking (immediate) and Non-Blocking (deferred) Assignments in Verilog
• Ports in Verilog Module
• Synthesis and Functioning of Blocking and Non-Blocking Assignments.
• Module Instantiation in Verilog

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Using Continuous Assignment to Model Combinational Logic in Verilog

In this post, we talk about continuous assignment in verilog using the assign keyword. We then look at how we can model basic logic gates and multiplexors in verilog using continuous assignment.

There are two main classes of digital circuit which we can model in verilog – combinational and sequential .

Combinational logic is the simplest of the two, consisting solely of basic logic gates, such as ANDs, ORs and NOTs. When the circuit input changes, the output changes almost immediately (there is a small delay as signals propagate through the circuit).

In contrast, sequential circuits use a clock and require storage elements such as flip flops . As a result, output changes are synchronized to the circuit clock and are not immediate.

In this post, we talk about the techniques we can use to design combinational logic circuits in verilog. In the next post, we will discuss the techniques we use to model basic sequential circuits .

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Continuous Assignment in Verilog

We use continuous assignment to drive data onto verilog net types in our designs. As a result of this, we often use continuous assignment to model combinational logic circuits.

We can actually use two different methods to implement continuous assignment in verilog.

The first of these is known as explicit continuous assignment. This is the most commonly used method for continuous assignment in verilog.

In addition, we can also use implicit continuous assignment, or net declaration assignment as it is also known. This method is less common but it can allow us to write less code.

Let's look at both of these techniques in more detail.

• Explicit Continuous Assignment

We normally use the assign keyword when we want to use continuous assignment in verilog. This approach is known as explicit continuous assignment.

The verilog code below shows the general syntax for continuous assignment using the assign keyword.

The <variable> field in the code above is the name of the signal which we are assigning data to. We can only use continuous assignment to assign data to net type variables.

The <value> field can be a fixed value or we can create an expression using the verilog operators we discussed in a previous post. We can use either variable or net types in this expression.

When we use continuous assignment, the <variable> value changes whenever one of the signals in the <value> field changes state.

The code snippet below shows the most basic example of continuous assignment in verilog. In this case, whenever the b signal changes states, the value of a is updated so that it is equal to b.

• Net Declaration Assignment

We can also use implicit continuous assignment in our verilog designs. This approach is also commonly known as net declaration assignment in verilog.

When we use net declaration assignment, we place a continuous assignment in the statement which declares our signal. This can allow us to reduce the amount of code we have to write.

To use net declaration assignment in verilog, we use the = symbol to assign a value to a signal when we declare it.

The code snippet below shows the general syntax we use for net declaration assignment.

The variable and value fields have the same function for both explicit continuous assignment and net declaration assignment.

As an example, the verilog code below shows how we would use net declaration assignment to assign the value of b to signal a.

Modelling Combinational Logic Circuits in Verilog

We use continuous assignment and the verilog operators to model basic combinational logic circuits in verilog.

To show we would do this, let's look at the very basic example of a three input and gate as shown below.

To model this circuit in verilog, we use the assign keyword to drive the data on to the and_out output. This means that the and_out signal must be declared as a net type variable, such as a wire.

We can then use the bit wise and operator (&) to model the behavior of the and gate.

The code snippet below shows how we would model this three input and gate in verilog.

This example shows how simple it is to design basic combinational logic circuits in verilog. If we need to change the functionality of the logic gate, we can simply use a different verilog bit wise operator .

If we need to build a more complex combinational logic circuit, it is also possible for us to use a mixture of different bit wise operators.

To demonstrate this, let's consider the basic circuit shown below as an example.

To model this circuit in verilog, we need to use a mixture of the bit wise and (&) and or (|) operators. The code snippet below shows how we would implement this circuit in verilog.

Again, this code is relatively straight forward to understand as it makes use of the verilog bit wise operators which we discussed in the last post.

However, we need to make sure that we use brackets to model more complex logic circuit. Not only does this ensure that the circuit operates properly, it also makes our code easier to read and maintain.

Modelling Multiplexors in Verilog

Multiplexors are another component which are commonly used in combinational logic circuits.

In verilog, there are a number of ways we can model these components.

One of these methods uses a construct known as an always block . We normally use this construct to model sequential logic circuits, which is the topic of the next post in this series. Therefore, we will look at this approach in more detail the next blog post.

In the rest of this post, we will look at the other methods we can use to model multiplexors.

• Verilog Conditional Operator

As we talked about in a previous blog, there is a conditional operator in verilog . This functions in the same way as the conditional operator in the C programming language.

To use the conditional operator, we write a logical expression before the ? operator which is then evaluated to see if it is true or false.

The output is assigned to one of two values depending on whether the expression is true or false.

The verilog code below shows the general syntax which the conditional operator uses.

From this example, it is clear how we can create a basic two to one multiplexor using this operator.

However, let's look at the example of a simple 2 to 1 multiplexor as shown in the circuit diagram below.

The code snippet below shows how we would use the conditional operator to model this multiplexor in verilog.

• Nested Conditional Operators

Although this is not common, we can also write code to build larger multiplexors by nesting conditional operators.

To show how this is done, let's consider a basic 4 to 1 multiplexor as shown in the circuit below.

To model this in verilog using the conditional operator, we treat the multiplexor circuit as if it were a pair of two input multiplexors.

This means one multiplexor will select between inputs A and B whilst the other selects between C and D. Both of these multiplexors use the LSB of the address signal as the address pin.

To create the full four input multiplexor, we would then need another multiplexor.

This takes the outputs from the first two multiplexors and uses the MSB of the address signal to select between them.

The code snippet below shows the simplest way to do this. This code uses the signals mux1 and mux2 which we defined in the last example.

However, we could easily remove the mux1 and mux2 signals from this code and instead use nested conditional operators.

This reduces the amount of code that we would have to write without affecting the functionality.

The code snippet below shows how we would do this.

As we can see from this example, when we use conditional operators to model multiplexors in verilog, the code can quickly become difficult to understand. Therefore, we should only use this method to model small multiplexors.

• Arrays as Multiplexors

It is also possible for us to use verilog arrays to build simple multiplexors.

To do this we combine all of the multiplexor inputs into a single array type and use the address to point at an element in the array.

To get a better idea of how this works in practise, let's consider a basic four to one multiplexor as an example.

The first thing we must do is combine our input signals into an array. There are two ways in which we can do this.

Firstly, we can declare an array and then assign all of the individual bits, as shown in the verilog code below.

Alternatively we can use the verilog concatenation operator , which allows us to assign the entire array in one line of code.

To do this, we use a pair of curly braces - { } - and list the elements we wish to include in the array inside of them.

When we use the concatenation operator we can also declare and assign the variable in one statement, as long as we use a net type.

The verilog code below shows how we can use the concatenation operator to populate an array.

As verilog is a loosely typed language , we can use the two bit addr signal as if it were an integer type. This signal then acts as a pointer that determines which of the four elements to select.

The code snippet below demonstrates this method in practise. As the mux output is a wire, we must use continuous assignment in this instance.

What is the difference between implicit and explicit continuous assignment?

When we use implicit continuous assignment we assign the variable a value when we declare. When we use explicit continuous assignment we use the assign keyword to assign a value.

Write the code for a 2 to 1 multiplexor using any of the methods discussed we discussed.

Write the code for circuit below using both implicit and explicit continuous assignment.

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Inertial & transport delays

Inertial delay.

Inertial delay models are simulation delay models that filter pulses that are shorted than the propagation delay of Verilog gate primitives or continuous assignments ( assign #5 y = ~a; )

​ COMBINATIONAL LOGIC ONLY !!!

Inertial delays swallow glitches sequential logic implemented with procedure assignments DON'T follow the rule

continuous assignments

procedure assignment - combinational logic

procedure assignment - sequential logic

As shown above, sequential logic DON'T follow inertial delay

Transport delay

Transport delay models are simulation delay models that pass all pulses, including pulses that are shorter than the propagation delay of corresponding Verilog procedural assignments

Transport delays pass glitches, delayed in time Verilog can model RTL transport delays by adding explicit delays to the right-hand-side (RHS) of a nonblocking assignment

nonblocking assignment

blocking assignment

It seems that new event is discarded before previous event is realized.

Verilog Nonblocking Assignments With Delays, Myths & Mysteries

Correct Methods For Adding Delays To Verilog Behavioral Models

Article (20488135) Title: Selecting Different Delay Modes in GLS (RAK) URL: https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1O3w000009bdLyEAI

Article (20447759) Title: Gate Level Simulation (GLS): A Quick Guide for Beginners URL: https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1Od0000005xEorEAE

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Why put delays in Verilog even for some simple assignment?

I found there are usually many delays in some Verilog source code even if on some simple statement, such as below. What's the underlying reason of placing such delay?

• 1 It's usually for gate-level simulation where you care about how long it takes for signals to propagate through digital logic in order to track down timing problems with the design. Is that what you're asking? –  godel9 Commented Nov 15, 2013 at 6:46
• @godel9 this makes sense. Then for gate level simulation, how to choose the right value for each operation/statement? –  Thomson Commented Nov 15, 2013 at 7:37

3 Answers 3

Your code isn't VHDL, or any other language I know about. It's presumably meant to be Verilog. In normal usage, you don't do a lot of manual delay specification in either language, and source code with delays in it is automatically generated by tools which write in the required delays (but not normally with delays like this). In older Verilog source code, though, you do frequently see a large number of '#0' delay specifications, as the scheduling model was historically broken.

It's usually for gate-level simulation where you care about how long it takes for signals to propagate through digital logic in order to track down timing problems with the design.

In order to choose the right value for each operation/statement, you would need timing information about the target device, usually from a datasheet or lab measurements.

If you don't have know or have access to this information, it's likely that you don't need this level of detail in your model. It's probably counter-productive to use anything other than actual values, since you'll end up with both false positives and false negatives when you're looking for timing problems.

For gate level verification I would hope that the library used for synthesis had been characterised and appropriate delays added to the base level components. Which would be used instead of the RTL in simulation. In Verilog there should be no need to added delays like this to RTL.

The delays may be added to testbench components to simulate off chip delays and interfaces, or delays between different synthesised sections. To calculate the correct delay requires knowledge of the final layout, length of track etc. External interfaces will specify max and minimum delays.

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